1. Field of Art
The disclosure generally relates to the emulation of circuits, and more specifically to promptly identifying unpredictable behavior of a digital system.
2. Description of the Related Art
Emulators have been developed to assist circuit designers in designing and debugging highly complex integrated circuits. An emulator includes multiple reconfigurable components, such as field programmable gate arrays (FPGAs) that together can imitate the operations of a design under test (DUT). By using an emulator to imitate the operations of a DUT, designers can verify that a DUT complies with various design requirements prior to a fabrication.
One aspect of emulation includes identifying functionality of a DUT. In one approach, identifying functionality of a DUT involves emulating a DUT and analyzing signals from the emulated DUT to verify improper, uncertain or unknown operations. For example, in case of power shut down or improper initialization, registers or logic circuits in the DUT are not properly terminated and states of those registers or logic circuits become unknown. During the operation of the DUT, the unknown states may cause improper logic operations, and the results of the improper logic operations may further affect other logic circuits to operate incorrectly throughout the DUT.
In a conventional approach, a digital signal is represented in a binary state (e.g., high or low) and identifying improper or unknown operations of the DUT involves performing emulation of the DUT until inappropriate or uncertain outcomes are detected at outputs of the DUT. In advanced processes (e.g., 22 nanometers (nm) and below), a DUT may include billions of logic circuits and signals. As a result, identifying unknown operations of a DUT may involve performing a large number of digital logic operations until improper logic operations are propagated at outputs because of unknown states, which may be a time consuming process. As a result, locating sources of unknown states and debugging them are inefficient.
Therefore, there is a need for an approach for identifying uncertainties of the operation of the DUT in a time efficient manner in terms of emulation cycles performed.